The present inventions relate to integrated circuit devices and processes, and particularly to CMOS devices and processes which are highly resistant to latchup.
Latchup
Latchup is one of the basic problems of CMOS technology. Consider the sequence of a PMOS source region, the surrounding N-well region, a p-well region (or p-type epitaxial layer), and an NMOS source region. This sequence of regions will inevitably occur in normal bulk CMOS designs, and it defines a thyristor. This thyristor is referred to as "parasitic," since it is not created intentionally. A thyristor is a bipolar device which has an extremely low on-resistance. Once the thyristor turns on (or "fires"), it will remain on for as long as it can draw its minimum holding current. This behavior is extremely undesirable in integrated circuits, since when such a parasitic thyristor fires it may destroy the integrated circuit (by drawing excessive current), or may rapidly discharge a portable system's battery, or may simply cause the chip to remain in a "stuck" condition, and hence become unusable, until the power supply is disconnected.
Any thyristor can be regarded as a merger of a PNP transistor with an NPN transistor, and this model is frequently a convenient way to analyze the properties of the parasitic thyristor. The gain of the parasitic thyristor is equal to the product of the gains of the bipolar transistors, so degrading the gain of either parasitic bipolar helps to degrade the parasitic thyristor. (Although the thyristor reaches low impedance once triggered, it is still useful to analyze the small-signal "gain" of the thyristor in considering triggering: lower gain will mean that a larger input energy is required to trigger the thyristor. Since voltage transients are always present, it is desirable to provide some margin of immunity against triggering by transients.) There are several ways to approach the device-level properties of the thyristor: either the holding current can be increased, or the firing voltage can be increased, or the gain of one or both of the parasitic bipolar transistors can be degraded, or low-resistance shunting elements can be added to bypass one or both of the parasitic bipolar transistors (so that the current driven by one transistor does not all appear as base current on the other).
Punchthrough
Another of the basic problems in normal CMOS (or almost any other field-effect transistor formed in bulk material) is punchthrough: when the depletion regions around the source/drain boundaries spread sufficiently to touch, then current can bypass the channel region, i.e. the source and drain are essentially shorted together.
Thin Film Transistors and Full Dielectric Isolation
An old goal in MOS processing has been to manufacture transistors which are separated from each other by dielectric layers, and not merely by reverse-biased junctions. However, this is not easy to achieve.
One way to obtain some of the advantages of full dielectric isolation is with thin-film transistors. Such transistors are fabricated with their channel regions in a deposited thin film layer (typically polycrystalline Si or SiGe). Thin-film transistors do provide full dielectric isolation, but they typically suffer from low mobilities and high junction leakage currents.
SOI and SIMOX
It has long been realized that silicon-on-insulator (SOI) structures, in which a layer of monocrystalline silicon overlies a layer of an insulator, would permit full dielectric isolation. Since the 1970s various techniques have been proposed for SOI, and many successful results have been published, but none of these techniques have remained in production use. (The nearest approach was the silicon-on-sapphire technology which was aggressively promoted by RCA.)
However, a new approach which was developed in the 1980s has begun to see mass production in the mid-1990s. This is the "SIMOX" approach, which uses high-dose oxygen implantation (followed by a significant anneal) to form a buried silicon dioxide layer under silicon which is still monocrystalline. Many articles have shown how to practice this process; see e.g. Isilkawa et al., "Formation mechanisms of dislocation and Si island in low-energy SIMOX," B91 NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH B 520 (1994); Li et al., effects of dose and target temperature on low energy SIMOX layers," 140 J. ELECTROCHEMICAL SOCIETY 1780 (1993); Nejim et al., "Direct formation of device worthy thin film SIMOX structures by low energy oxygen implantation," B80-81 NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH B 822 (1993); Li et al., "The effects of dose and target temperature on low energy SINFOX layers," PROCEEDINGS OF THE FIFTH INTERNATIONAL SYMPOSIUM ON SILICON-ON-INSULATOR TECHNOLOGY AND DEVICES 368 (1992); Reimbold et al., "Aging analysis of nMOS of a 1.3-.mu.m partially depleted SIMOX SOI technology comparison with a 1.3-.mu.m bulk technology," 40 IEEE TRANS'NS ELECTRON DEVICES 364 (1993); Usami et al., "Evaluation of bonding silicon-on-insulator films with deep-level transient spectroscopy measurements," E75-C IEICE TRANS'NS ELECTRONICS 1049 (1992); Takao et al., "Low-power and high-stability SRAM technology using a laser-recrystallized p-channel SOI MOSFET," 39 IEEE TRANS'NS ELECTRON DEVICES 2147 (1992); Nakashima et al., "Buried oxide layers formed by low-dose oxygen implantation," 7 J. MATERIALS RESEARCH 788 (1992); Barklie et al., "E'.sub.1 centres in buried oxide layers formed by oxygen ion implantation into silicon," B65 NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH B 93 (1992); Bae et al., "The effects of annealing conditions on the characteristics of SIMOX SOI," 28A J. KOREAN INSTITUTE OF TELEMATICS AND ELECTRONICS 54 (1991); Visitserngtrakul et al., "Mechanisms of defect formation and evolution in oxygen implanted silicon-on-insulator material," in MICROSCOPY OF SEMICONDUCTING MATERIALS 1989 at 557; Lacquet et al., "Ultraviolet reflectance of room temperatures nitrogen implanted silicon (SOI)," 1989 IEEE SOS/SOI TECHNOLOGY CONFERENCE at 110; Fechner et al.; "Physical characterization of low defect SIMOX materials," 1989 IEEE SOS/SOI TECHNOLOGY CONFERENCE at 70; De Veirman et al., "Defects in high-dose oxygen implanted silicon," 38-41 MATERIALS SCIENCE FORUM 207 (1989); Cristoloveanu, "Electrical evaluation of SIMOX material and integrated devices," in SILICON-ON-INSULATOR AND BURIED METALS IN SEMICONDUCTORS at 335 (ed. Sturm et al. 1988); Scanlon et al. "Evidence for oxygen concentration changes induced by low-temperature 0-18 implantation into a SIMOX buried-oxide layer," in SILICON-ON-INSULATOR AND BURIED METALS IN SEMICONDUCTORS at 141 (ed. Sturm et al. 1988); de Veirman et al., "HVEM and electrical characterisation of SIMOX structures," in SILICON-ON-INSULATOR AND BURIED METALS IN SEMICONDUCTORS at 129 (ed. Sturm et al. 1988); Nieh et al., "Formation of buried oxide in MeV oxygen implanted silicon," in SILICON-ON-INSULATOR AND BURIED METALS IN SEMICONDUCTORS at 73 (ed. Sturm et al. 1988); Sioshansi et al., "Processing SIMOX wafer below the critical temperature," in SILICON-ON-INSULATOR AND BURIED METALS IN SEMICONDUCTORS at 67 (ed. Sturm et al. 1988); Stoemenas, "Silicon on Insulator Obtained by High Dose Oxygen Implantation, Microstructure, and Formation Mechanism," 142 J. ELECTROCHEM. SOC. 1248 (1995); and Auberton-Herve et al., "SOI substrates for low-power LSIs," SOLID-STATE TECHNOLOGY, March 1995, at 87. All of these publications, and all of the references cited in them, are hereby expressly incorporated by reference. Note that some of this work has shown that implantation of nitrogen rather than oxygen can be used to form the buried dielectric layer.
Innovative CMOS Device and Process
One of the basic goals in the fabrication of thin film MOS transistors is to obtain the performance of MOS transistors that have been fabricated in single crystal silicon together with device-to-device isolation. The disclosed innovations allow the fabrication of dielectrically isolated thin film MOS transistors as well as other devices with both of these features.
The present application provides a CMOS device and process in which the source/drain and channel regions are fully dielectrically-isolated from the underlying silicon. This source/drain regions may be polysilicon, or may be recrystallized into monocrystalline material.
The parent application described a process device structure in which the source/drain regions (but not the channels) were separated from the substrate by underlying dielectric layers. The present application describes a modified process and device structure, in which the monocrystalline channel region, as well as the source/drain regions, are dielectrically isolated from the substrate. The substrate defines a crystal lattice for growth or recrystallization of the channel region, but thereafter is separated from the channel region by an oxygen implant which creates a buried oxide layer which creates full dielectric isolation. This results in a fully dielectrically-isolated structure, in which there is no possibility whatsoever of junction spiking or latch-up.
The parent application describes the fabrication of MOS transistors with sources and drains made in polysilicon, but with the channel region formed in monocrystalline silicon. The channel regions of MOS transistors fabricated in this fashion are common with the substrate. However, by implanting a high dose of oxygen, followed by the proper anneal step, a layer of silicon dioxide will be formed that separates the silicon channel region from the underlying substrate.
This technique can also be used to fabricate diodes and lateral bipolar transistors that have their junctions in the region of single crystal silicon. (In the bipolar transistor the device is lateral, with the base region also formed of single-crystal silicon.)
This technology differs significantly from conventional SIMOX technology, which uses ion implantation of oxygen to obtain dielectric isolation. In the present technology, the percentage of chip area that must be successfully annealed following the oxygen implant step is relatively low (just the area that has silicon exposed just prior to deposition of the first polysilicon layer). This reduction in the area requiring successful recrystallization increases the likelihood that the chip will operate as intended.
This technology can be combined with various process sequences for manufacturing discrete devices, conventionally integrated circuits, and power integrated circuits. This technology also retains the advantages described in the parent application.
Thus features and advantages of various embodiments of the disclosed inventions include:
1. This structure reduces the capacitance between the body and both the source and the drain. PA0 2. The spacings between the diffused source/drain regions can be reduced, since these diffused regions are in polysilicon, and can be laterally separated by etching. PA0 3. Contact spiking through source/drain regions is no longer a concern, since all source/drain regions now have a layer of dielectric beneath them. PA0 4. Susceptibility to latch-up is reduced, since the source/drain diffusions are not in contact with the body regions. PA0 5. The process steps used to provide the structures can be included in a more complex process sequence such as BiCMOS technology. PA0 6. The basic structure can be used in a variety of technologies, including NMOS, PMOS, CMOS, DMOS, or JFET.
Note that the edge of the oxide which defines the active region is not self-aligned to the gate in the second polysilicon layer. This introduces an additional design parameter. For instance, by making the second polysilicon gate wider than the oxide opening which defines the width of the crystalline silicon region, a degree of underlap is achieved which may cause a region of more lightly doped silicon, having a doping determined by lateral diffusion which becomes lighter going from the drain to the channel, and thus automatically provides a lightly doped drain profile to reduce hot carrier effects. Manipulation of this kind can be used in combination with the conventional side-wall-oxide-defined LDD regions, or even with a conventional double-diffused graded drain (formed by differential diffusion of phosphorous plus arsenic). Unlike the conventional LDD and graded drain techniques, this new technique permits ASYMMETRY in the transistor, in that the source and drain regions do not have to have exactly the same profile. Thus the potential contour of the drain boundary can be optimized without adding series resistance on the source side.
The thickness of the oxide which is used to determine the size of the monocrystalline silicon region is not critical. Thus, again, the thickness of this oxide can be determined by other considerations. For example, in smart power processes, the oxide layer can be used for the gate oxide of VDMOS or LDMOS high voltage and/or high-current transistors.
In one class of embodiments, this device structure can be used for just one of the device types in a CMOS integrated circuit. For example, by making the PMOS devices, but not the NMOS devices, in the poly1/epi layer, the NMOS and PMOS devices can actually be overlapped with each other. (The removal of the PMOS devices from the substrate is enough to inhibit latchup.) Thus, this provides significant advantages in density.
Further advantages in density are provided by the improved tolerance to contact misalignment. In conventional structures, misalignment of a contact to the active area may result in etching through the corner of the field oxide to expose the channel stop diffusion (and thus potentially cause a short circuit). Similarly, a misaligned contact to polysilicon over active may make contact to the source/drain region. Normally design rules are selected to make these mishaps adequately unlikely, but the present invention permits these design rules to be relaxed (and hence improves density and/or yield).
In the presently preferred embodiment, the oxide which is used to define apertures where crystalline material will be grown is not itself field oxide, but is used in combination with a LOCOS field oxide which covers the margins of the P-well and N-well regions. Alternatively, various other techniques for field isolation can be used, or it may even be possible to eliminate the field oxide (IF the combination of on-chip voltages, dielectric thickness under the polysilicon lines, and substrate doping under the polysilicon lines combine, according to well-known formulas, so that the parasitic transistors do not turn on).
In a further class of embodiments, the same process flow can be used to provide a self-aligned channel stop implant. To implement this, a channel stop implant is performed (with an energy which is selected to reach through the oxide thickness) after the gate structure in poly-2 is in place. (Depending on the desired lateral spacing of the channel stop diffusions, this implant can be performed with or without sidewall spacers on the gate.) This technique provides an important further step toward a process with no conventional "thick field-oxide" at all. Such a process can provide the important advantages of reduced topography, reduced diffusion length of buried layers, and reduced process complexity.